1. Field of the Invention
The invention relates generally to the design and fabrication of semiconductor devices and, more particularly, to the design and fabrication of an integrated circuit (IC) device that comprises electrostatic discharge (ESD) protection in the form of an integral bipolar junction transistor (BJT).
2. Related Art
As semiconductor device technology continues the seemingly ineluctable evolution into and beyond the realm of submicron feature sizes, a number of aspects of device operation have assumed substantially increased significance. For example, advanced complementary metal oxide semiconductor (CMOS) devices, in which thin gate oxides and low drain/substrate breakdown voltages now prevail, are especially vulnerable to ESD events. ESD commonly occurs when an IC device comes in contact with or in proximity to an object that is charged to an electrostatic potential that differs substantially from the electrostatic potential of the device in question. During an ESD event, charge is transferred within a short period of time between one or more pins on an IC package and the exogenous charged object. Typically, the duration of an ESD pulse is less than one microsecond. The charge transfer is accompanied by a transient voltage and/or current that is often adequate to break down or at least damage the gate oxide layer of active MOS devices internal to the IC. The ESD transient may also precipitate electro-thermal failures, such as contact spiking, silicon melting or interconnect discontinuities. Consequently, IC products judiciously include internal ESD protection circuits as a prophylaxis against ESD events that result from contact with human beings, machine handling in fabrication, assembly and testing, and environmental conditions. (Operation of semiconductor devices in an automotive environment is recognized to be especially hostile from an ESD perspective.)
The magnitude of ESD phenomena as a threat to semiconductor device reliability is reflected in the attention attracted in the technical literature. See, for example, Ajith Amerasekera and Charvaka Duvuury, ESD in Silicon Integrated Circuits (2nd Ed.), John Wiley & Sons (2002); Albert H. Wang, On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective, Kluwer Academic Publishers (2002).
Perhaps the most common protection scheme encountered in CMOS ICs is based on the parasitic BJT that is associated with an nMOS transistor. Consonant with this approach, the drain of the associated pMOS transistor is connected to an IC pin that is to be protected, and the associated nMOS source is coupled to GND. (In this context, GND may be understood to be any reference node that serves as a current sink, regardless whether the voltage potential of the node is 0V.) The ESD protection threshold is dependent on the width of the nMOS transistor from drain to source under the gate oxide. When an ESD event occurs, operation of the parasitic BJT is driven into its snapback region, and the BJT conducts current from the protected pin to GND, thereby diverting the ESD energy away from other devices internal to the IC. An ESD protection device predicated on the above configuration is depicted in FIG. 1.
As may be seen in FIG. 1, relevant portions of a conventional ESD protection device that may be incorporated into an IC product include an N-type epitaxial layer 11 that has been formed on a substrate (not shown). A P-type base 12 is formed in epitaxial layer 11, as is a deep N-type collector region 13. A highly doped P+ base extension 14 effectively defines the lateral (i.e., horizontal) spacing between the base and collector regions.
Processing techniques used to fabricate ESD protection device 10 are a matter of a priori knowledge to skilled practitioners and will not be discussed in detail here. Suffice it to say that various photolithographic, implantation and diffusion steps may be involved. However, it is important to appreciate that the formation of collector region 13 and base regions 12 and 14 require at least two distinct photolithographic patterning steps and, concomitantly, two distinct mask layers. As may be readily comprehended from FIG. 1, the spacing (indicated by the literal “S” in FIG. 1) between base regions (12,14) and collector region 13 is established indirectly, as a function of the base and collector region geometries. Therefore, variations in the registration or alignment of the base and collector masks, or variations in dimensions of those masks per se, are translated into variations in the spacing, S, between the base and collector regions. Because operation of ESD protection device 10 is predicated on the occurrence of breakdown between the base and collector regions as a result of an ESD event, the spacing dimension is a critical determinant of the ESD protection threshold.
To wit: an ESD event (assume here a positive-going voltage transient) causes the bias at collector region 13 to increase dramatically. As a result, a space-charge region 15 is created that advances and extends horizontally across epitaxial region 11 from the base regions (12,14) in the direction of the collector region 13. At some point, a critical electric field is established at the perimeter of P+ base region 14, and breakdown is initiated. Eventually, the effective collector/base junction of the BJT becomes forward biased so that a snapback condition occurs, resulting, equivalently, in the formation of a Zener diode between the base and collector regions. The Zener diode then presents a low-impedance path for the ESD current. In this manner, the ESD current and voltage are diverted from the IC and conducted to GND by the Zener diode.
In the operation of an ESD protection device such as described above, the triggering voltage at which breakdown initially occurs is of appreciable importance. Because the triggering voltage, or ESD threshold, is generally coincident with the creation of the critical electric field between the base and the collector regions, the triggering voltage is controlled by, e.g., is generally inversely related to, the spacing dimension. From one perspective, controllability of ESD triggering in this fashion is a salutary feature of an ESD device such as ESD protection device 10. However, because the spacing dimension is dependent on the relationship between at least two masking steps, it is especially susceptible to fabrication process tolerances and variations. Therefore, the design of the ESD protection device must accommodate such variations in a manner that assures reliability in the face of ESD events. Inevitably, the accommodation of such generous tolerances results in a design that occupies more than the minimal amount of semiconductor real estate. Furthermore, the inherent variations alluded to above impede the transportability of the fabrication process from one manufacturing facility to another.
Accordingly, what is desired is an ESD protection technique that tends to minimize variations in the ESD triggering point so that tighter tolerances may be maintained in a given fabrication process and so that a fabrication process may be transported in tact from one manufacturing facility to another. Tighter tolerances in the ESD triggering point are significant also for the degree in which conservation of semiconductor area is thereby achieved.
Skilled artisans appreciate that elements in Drawings are illustrated for simplicity and clarity and have not (unless so stated in the Description) necessarily been drawn to scale. For example, the dimensions of some elements in the Drawings may be exaggerated relative to other elements to promote and improve understanding of embodiments of the invention.